A CMOS image sensor has been proposed that includes a pixel portion with multiple pixels arranged in a two-dimensional array in which image signals read from each pixel in this pixel portion are read sequentially per pixel column, and CDS or other processing is conducted on each column signal to be converted to and output as an image signal.
The CMOS image sensor has a floating diffusion (FD) amp including floating diffusion for each pixel. The output is normally a parallel column output type in which a certain row is selected in the pixel array and then simultaneously read in the column direction.
This is because it is difficult to obtain sufficient drive power from the 1-1) amp arranged in the pixel, which makes it desirable to lower the data rate and advantageous to use parallel processing.
Many different kinds of image signal reading (output) circuits for parallel column output type of CMOS image sensors have been proposed.
One of the most advanced forms of these is a type that is provisioned with an analog digital converter (hereinafter, referred to as ADC) per column to retrieve digital image signals.
CMOS image sensors equipped with such parallel column type of ADCs are disclosed, for example, in Non-Patent Literature 1 and Patent Literature 1.
FIG. 1 is a block diagram illustrating an example configuration of a solid imaging device (CMOS image sensor) equipped with parallel column ADCs.
As illustrated in FIG. 1, a solid imaging device 1 includes a pixel portion 2, a vertical scanning unit 3, a horizontal transfer scanning unit 4, and a column processing circuit group 5 made from a group of ADCs.
The solid imaging device 1 further includes a digital-analog converter (hereinafter, referred to as a DAC) 6 and an amp circuit (S/A) 7.
The pixel portion 2 is configured with a unit pixel 21, which includes a photodiode (photoelectric conversion element) and an internal pixel amp, arranged in a matrix form.
A column processing circuit 51 forming the ADC for each column are arranged in multiple columns in the column processing circuit group 5.
Each column processing circuit (ADC) 51 includes a comparator 51-1 that compares a reference signal RAMP (Vslop), which is a ramp waveform generated by the DAC 6 in which the reference signal changes in steps, and an analog signal obtained via a vertical signal line from pixels per row line.
Each column processing circuit 51 also includes a counter latch 51-2 that counts the comparison time of the comparator 51-1 and stores this count results.
The column processing circuit 51 includes a function to convert an n-bit digital signal and is disposed per vertical signal line (column line) 8-1 through 8-n, which configures the parallel column ADC block.
The output from each memory 51-2 is connected to a horizontal transfer scanning line 9 with a width of k bits, for example.
A k number of amp circuits 7 are arranged corresponding to the horizontal transfer scanning line 9.
FIG. 2 is a diagram illustrating a timing chart for the circuit in FIG. 1.
The analog signal (potential Vsl) read from the vertical signal line 8 is, for example, compared to the reference signal RAMP (Vslop) that changes in steps by the comparator 51-1 arranged per column in each column processing circuit (ADC) 51.
At this time, the levels of the analog potential Vsl and the reference signal RAMP (Vslop) intersect, which is counted by the counter latch 51-2 using a reference clock CK until the output of the comparator 51-1 inverts. As a result, the potential (analog signal) Vsl of the vertical signal line 8 is converted into a digital signal (AD conversion). In this case, the counter is configured as a full-bit ripple counter.
This AD conversion is performed twice per read.
For the first conversion, the reset level (P phase) of the unit pixel 21 is read by the vertical signal line 8 (-1 through -n), and AD conversion is executed.
Variances between pixels are included in this reset level P phase.
For the second conversion, the signal photoelectrically converted by each unit pixel 21 is read (D phase) by the vertical signal line 8 (-1 through -n), and AD conversion is executed.
Variances between pixels are also included in this D phase, and so correlated double sampling (CDS) may be implemented by executing the operation of subtracting the P phase level from the D phase level (D phase level-P phase level).
The converted digital signal is recorded by the counter latch 51-2, sequentially read by the horizontal (column) transfer scanning circuit 4 to the amp circuit 7 via the horizontal transfer scanning line 9, and ultimately output.
Parallel column output processing is performed in this way.